Sources for figures on this site
Figures below come from published industry sources and are shown as typical ranges. Individual projects vary.
~50% first-pass EMC failure; 5–7% on retest
Intertek white paper "Why 50% of Products Fail EMC Testing the First Time" (Roland Gubisch), which reports failure rates continuing to run around 50% and a third-trial failure rate of 1–2%. Rheintech, citing the same paper, gives 5–7% on the second trial once root causes are understood.
$28k–$46k per PCB respin
Lifecycle Insights PCB design surveys, as reported in trade press. Different outlets attribute different values to the same study (about $28,500 and about $44,000–$46,000 per respin), so we show the range. EMA Design Automation independently estimates $10k–$50k per iteration for moderately complex boards. Several of these sources are published by EDA vendors.
3–4+ weeks of schedule after a failed compliance test
LA NPDT puts a respin at 3–4 weeks for simple boards. EMA Design Automation’s worked example assumes a one-month delay.
$1k–$10k per day for external EMC lab time
Tektronix cost table published by Interference Technology, and Keysight’s EMC testing guide. Both companies sell pre-compliance equipment.
An early design change costs in the low thousands; far more near production
PSMA newsletter (Q4 2019) and How2Power (Sept 2019), both citing a Sunpower cost-of-change graph. The direction is well supported; the exact figures are dated.
Many of these figures are published by EDA vendors, test-equipment makers, or labs, and some are several years old. We use them as typical ranges, not as predictions for any one project.